The present invention relates to functional level design of an integrated circuit, and more particularly, it relates to pipelined circuit synthesis and a functional module model used in the synthesis.
A pipeline architecture is utilized for attaining a high speed operation of an electronic circuit. A method of pipelining a general circuit is described in detail in "Principles of Digital Design" (written by Gajski published by Prentice Hall).
In the pipelining, pipeline registers are inserted on signal paths, so that computation can be executed in parallel in respective areas partitioned by the pipeline registers.
FIGS. 14(a) and 14(b) are diagrams for illustrating the basic concept of the pipelining, wherein FIG. 14(a) is a given circuit diagram and FIG. 14(b) is a diagram resulting from the pipelining of the circuit of FIG. 14(a). In FIGS. 14(a) and 14(b), a reference numeral 310 denotes a symbol model of an operator (module) and a reference numeral 320 denotes a symbol model of a pipeline operator. In FIG. 14(a), positions where the pipeline registers can be inserted are positions 330 on signal paths between the operators 310 and 320 and a pipeline register insertion position 340 previously set in the pipeline operator 320.
In FIG. 14(b), four pipeline registers 350 are inserted in the circuit of FIG. 14(a). Respective data data(i) through data(i+6) are successively transferred through the areas partitioned by the pipeline registers 350 in every clock period. When the delays of the areas partitioned by the pipeline registers 350 are indicated as ds1, ds2 and ds3, respectively, the clock period of this circuit can be shortened to max(dsi), namely, the maximum value among the delays ds1, ds2 and ds3.
When the number of pipeline steps is indicated as N, the clock period can be ideally shortened to 1/N of the initial processing time. When the number of data is indicated as M, the data can be processed in a time period as short as (M+N-1)/N of the original processing time. When M is sufficiently larger than N, the pipelining can realize an operation speed of approximately N times as high as the original speed.
However, the pipeline register insertion positions are conventionally limited to signal paths between the operators and the previously set positions in pipeline operators. Accordingly, the delays of the respective areas partitioned by the pipeline registers cannot be equalized. It is when the delays of the respective areas partitioned by the pipeline registers are equal that the clock period can be shortened to 1/N of the original processing time. However, since the delays of the areas cannot be equalized by the conventional technique, the clock period cannot be sufficiently optimized.
Furthermore, the delay and the area of each module are fixed because the layout design has already been completed. Therefore, for example, when one area partitioned by the pipeline registers has a margin in its delay against the clock period, the setting of the delay and the area size of this area cannot be changed.
In this manner, optimal pipelining has not been realized by the conventional technique.